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Jobs that require tcl (programming language) skill

INTEL MOBILE COMMUNICATIONS SOUTH EAST ASIA PTE. LTD.
20Mar
Jr0100259 Sr Digital Rtl2Gds Engineer
INTEL MOBILE COMMUNICATIONS SOUTH EAST ASIA PTE. LTD.   via JobsCentral



Roles & Responsibilities

Creates bottoms up elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUB level floor plans, abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a    Read more

wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.

Requirements

5 to 10 years experience in complex Digital SOC design

Must be proficient in Digital Implementation (synthesis, Static timing analysis, timing constraint development, UPF, ...)

Experience in interacting with Backend Engineers to drive the best implementation, hands on experience with Place and Route tool is a plus

Must be proficient in scripting languages (TCL, Python)

Skills
Realtek Singapore Private Limited
20Mar
Physical Design Engineer_Senior Physical Design Engineer
Realtek Singapore Private Limited   via JobsCentral



Job Description

Provide back-end design support to the various business units.

Take charge of floorplanning, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antanna).

Active participation in working with fronted and integration team.

Job Requirement

Bachelor Degree or above in Electrical Engineering in EDA (Electronic Design Automation), back-end physical design and verification.

Familiar with hierarchical physical design strategies, methodologies and deep sub-micron    Read more

technology issues.

Familiar with back-end physical design flow, mainly floorplanning, congestion analysis, placement optimization, clock-tree synthesis and timing closure.

Proficient in programming/scripting with good coding experience in Tcl/Perl/Python/Tk.

Processes good working ethic, good verbal and written communication skills.

Familiar with tools such as Synopsys IC Compiler/Cadence SoC Encounter and Primetime.

Good knowledge on static timing analysis (PrimeTime), EM/IR-Drop/crosstalk analysis (PTSI,Redhawk), formal or physical verification (Calibre) will be a plus.

Singaporeans are welcome to apply.

Skills
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
18Mar
Smts Design Enablement
GLOBALFOUNDRIES SINGAPORE PTE. LTD.   via JobsCentral



Roles & Responsibilities

As an SMTS Design Enablement Engineer, you will be a member ofthe Design Enablement Team responsible for developing design components for Mainstream Process Design Kits (PDK).

Develop process design kit (PDK) components, specifically decks for design rule checking (DRC) and deliver as per schedules.

Engineer and validate PDK component requirements via interlock with others, e.g. Ground Rule and Device engineers.

Validate PDK component implementation with automated and manual quality    Read more

checks.

Develop methods and/or scripts to improve PDK component efficiency or accuracy.

Work with other cross functional teams to develop new PDK offerings or PDK updates.

Mentor and lead a team of engineers for major PDK development projects.

Interface with customers on PDK related topics and provide timely response to advise or resolve customer questions and concerns.

Requirements

Bachelor’s Degree in Electrical Engineering, Microelectronics, or equivalent.

Minimum of 10 years of work experience in semiconductor and/or EDA industries.

Demonstrated hands on PDK developer-level experience in the development and testing of DRC rule files.

Solid understanding of semiconductor processes in advanced technology nodes (28nm and below).

Ability to interpret complex design rules.

Excellent technical problem solving skills.

Hands on experience in TCL and shell programming.

Outstanding communication skills – both written and verbal; demonstrated ability to communicate at various levels within an organization.

Good attitude and interpersonal skills, tactful and works well in team environment.

Self-motivated, resourceful, shows initiative and needs minimum supervision.

Well organized and exhibits attention to detail.

Working knowledge of software test techniques.

Experience with Mentor Calibre physical verification tools.

Experience with Advanced DRC topics (e.g. Antenna checks, ESD, Latchup, Decomposition techniques, etc).

Familiarity with Cadence Virtuoso tools and SKILL language is preferred.

Familiarity with GLOBALFOUNDRIES process technology is preferred.

Skills
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
18Mar
Mts Design Enablement
GLOBALFOUNDRIES SINGAPORE PTE. LTD.   via JobsCentral



Roles & Responsibilities

Responsibilities:

Develop LVS runsets to the major tools used by customers.

Validate LVS runsets or any peripheral kit element to ensure quality delivery.

Support customer feedback and provide timely response to advise or resolve customer questions and concerns.

Perform integration testing with cdslibs/LVS/PEX/SpiceModel to ensure proper integration of process design kit components.

Review and interpret process design rules and spice model documents, to create specification data for PDK development.

Requirements

8-12 Years    Read more

of Experience with a good degree

Fluency in English Language - written & verbal

The engineer must possess good engineering knowledge, excellent with programming languages like C, perl, tcl/tk and semiconductor device layout knowledge.

He/She should also be experienced with industry standard design/layout tools and design kits and be skilled in design kit development.

He/She should provide technical leadership to colleagues/team members, be able to identify areas for improvement and strive for continuous improvement in team delivery.

Skills
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
18Mar
Principal Engineer Design Enablement
GLOBALFOUNDRIES SINGAPORE PTE. LTD.   via JobsCentral



Roles & Responsibilities

Responsibilities:

Develop LVS runsets to the major tools used by customers.

Validate LVS runsets or any peripheral kit element to ensure quality delivery.

Support customer feedback and provide timely response to advise or resolve customer questions and concerns.

Perform integration testing with cdslibs/LVS/PEX/SpiceModel to ensure proper integration of process design kit components.

Review and interpret process design rules and spice model documents, to create specification data for PDK development

Requirements

8-12 Years of    Read more

Experience with a good degree

Fluency in English Language - written & verbal

The engineer must possess good engineering knowledge, excellent with programming languages like C, perl, tcl/tk and semiconductor device layout knowledge.

He/She should also be experienced with industry standard design/layout tools and design kits and be skilled in design kit development.

He/She should provide technical leadership to colleagues/team members, be able to identify areas for improvement and strive for continuous improvement in team delivery.

Skills
EPS Computer Systems Pte Ltd
16Mar
Library Characterization Engineer
EPS Computer Systems Pte Ltd   via JobsCentral



Roles & Responsibilities

Standard-Cell & I/O timing model characterization and generation

Standard-Cell & I/O library Front-End/Back-End design kit generation, including LIB, verilog, IBIS, LEF and Milkywayetc

Library characterization, validation flow development and maintenance

HOW TO APPLY:

Interested applicants, please submit your updated resume in MS Word format to [Click Here to Email Your Resume]

Please state your availability, current & expected salaries for processing purpose.

All applications will be treated in the strictest confidence.

We    Read more

regret that only shortlisted candidates will be notified.

Requirements

Bachelor/Masters Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science

Experience in timing modeling tool, e.g. Liberate/Siliconsmart

Experience in Spectre/Hspice, Virtuoso schematic, layout experience is a plus

Proficient in script programming with Perl, Tcl or PythonHOW TO APPLY:

Interested applicants, please submit your updated resume in MS Word format + Recent Photo to [Click Here to Email Your Resume]

Please state your availability, current & expected salaries for processing purpose.

All applications will be treated in the strictest confidence.

We regret that only shortlisted candidates will be notified.

AiLin Lee | EA Registration No: R1104629

Skills
EPS Computer Systems Pte Ltd
16Mar
Physical Design Engineer
EPS Computer Systems Pte Ltd   via JobsCentral



Roles & Responsibilities

Fully responsible for Netlist-to-GDS physical design implementation of low power chips

Responsible for physical design, development for variety of SoC(System On Chip) and tapeout.

Execute state-of-art methodologies include, floor-planning, place and route, RC extraction, timing and power optimization, physical verification.

Doing benchmarking on Performance/Power/Area to validate the robustness of APR flow.

Enhance project efficiency by using Perl, TCL, Python etc.

Requirements

Bachelor/Masters Degree in Electrical/Computer Engineering

Minimum 5 years of relevant working experience

Experience    Read more

in physical design with tape-outs

Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or Encounter

Good in script programming with Perl, TCL/TK or other languages

Interested applicants, please send your updated resume in MS WORD format to [Click Here to Email Your Resume] for immediate processing. Do include your availability, last drawn & expected salary. We regret that only shortlisted candidates will be notified. Thank you.

Jia Ling l R1872250

Skills
EPS Computer Systems Pte Ltd
16Mar
Memory Development & Automation Engineer
EPS Computer Systems Pte Ltd   via JobsCentral



Roles & Responsibilities

Memory Timing Characterization, Physical Verification, Compiler Porting and Model Verification

Strong focus on design automation for memory compiler

Develop & perform timing, power & noise collaterals characterization flow

Perform quality assurance check on deliverable design kits

Requirements

Bachelor/Masters Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science

Knowledge of SRAM/ROM memory functionality and high speed, low power memory design architecture is a plus

Proficient in script programming with Perl, Tcl or Python

Interested applicants,    Read more

please send your updated resume in MS WORD format to [Click Here to Email Your Resume] for immediate processing. Do include your availability, last drawn & expected salary. We regret that only shortlisted candidates will be notified. Thank you.

Jia Ling l R1872250

Skills
TEK VILLAGE PTE. LTD.
15Mar
Baseband Engineer
TEK VILLAGE PTE. LTD.   via JobsCentral



Roles & Responsibilities

We are seeking a Baseband Engineer with strong capabilities in wireless system design. The candidate will need to understand the DSP design process and tools used on FPGA systems. The candidate will be able to simulate algorithms to verify performance on tools such as Matlab/Simulink, then integrate and test the design on a prototype. The candidate will have a thorough understanding of VHDL, FPGA toolchains and    Read more

lab equipment for physical layer validation. The candidate will need to generate peer review, design memos, interface control requirements and test plans.

Designing and developing signal processing algorithms and wireless communication systems

Conducting simulations on end-to-end system under various RF impairments and channel fading conditions

Working closely with product and team to develop solutions that meets system requirements

Participating in prototype bring-up, performance characterization and optimization

System integration, field testing and verifying product performance with lab equipment

Requirements

Diploma/Bachelor/Master Degree/Ph.D in Electronics an Electrical Engineering/computer science with an emphasis in wireless digital communication or equivalent

Proficiency in RTL in VHDL/Verilog

Proficiency with FPGA design tools such as ISE, Vivado and SDSOC

Familiarity with latest Xilinx FPGA technologies such as 7 series or Zynq/Ultrascale+

Experience in generating FPGA architecture for high speed, multiple clock domain designs

Experience in FPGA optimizing, synthesizing and executing timing closure;

Excellent written and verbal communication skills

Strong mathematical, analytical and problem-solving skills

Thorough, disciplined, methodical, and good documentation habits

Able to work independently as well as within a multi-cultural team spread

Knowledge in advanced wireless communications technique such as beamforming, synchronization, adaptive equalization, error correction techniques and RF system analysis

Proficiency in Matlab with signal processing and communication tool box

Proficiency in ModelSim on generating testbench for verifications

Proficiency in scripting language such as Python/TCL

Experience with peripheral interfaces (UART, I2C, SPI, SDIO, Ethernet, PCI Express, etc)

Experience with high speed interfaces like SERDES, AXI and DDR in FPGA

Competency with RF/Wireless tests and measurement lab equipmentsuch as logic analyzer, spectrum analyzer and vector scalar analyzer

Preferred Skills, Experiences and Knowledge

Knowledge in wireless communications system, signal processing techniques and RF system analysis

Experience in Matlab simulation, RTL coding, Modelsim test bench and Xilinx FPGA toolchains

Familiar with lab equipment measurement in time, spectral domain and vector signal analysis

Skills
INTEL MOBILE COMMUNICATIONS SOUTH EAST ASIA PTE. LTD.
15Mar
Jr0099400 Digital Design Engineer (Open)
INTEL MOBILE COMMUNICATIONS SOUTH EAST ASIA PTE. LTD.   via JobsCentral



Roles & Responsibilities

The main areas of responsibility as Digital Design Engineer include but not limited:

Register-transfer level (RTL) coding in VHDL/Verilog

Functional simulation and block-level cerification

RTL design quality checking

Code coverage analysis

Design/Database environment development

Requirements

Candidates should have a BS or MS degree in Electrical Engineering, Computer Engineering or equivalent related field.

Good knowledge in digital logic design.

Familiar with RTL design language - Verilog/VHDL

Familiar or experience on following EDA tools or similar:

Spyglass for linting,    Read more

RDC/CDC

Simulation tool: NCSIM or/and VCS

Programming/Script language, for example, C, C Shell, Python, TCL

Good communication skills and problem-solving skills

Skills